In general, an integrated circuit for digital operations is equipped with a control signal producing circuit for sequential functions of the component circuits, and a source of voltage is shared by the control signal producing circuit and the component circuits. When the integrated circuit incorporated in an electronic system is activated upon a power switch-on event, the source of voltage is unstable in voltage level, so that the control signals are irregularly produced by the control signal producing circuit These irregular control signals mislead the sequential functions of the component circuits, which sometimes results in serious problems in the integrated circuit For example, data output terminals are provided in association with wired-OR gates, respectively, which are supplied with one of the control signals such as an enable signal In this arrangement, if the control signal is stable, conduction paths are liable to take place in the wired-OR gates and, for this reason, a large amount of current flows into the ground terminal, thereby causing the electronic system to fall into failure. For preventing the integrated circuit from the consumption of a large amount of current, a disenabling circuit is provided in the integrated circuit, and the disenabling circuit is operative to cause the component circuits to stay in the inactive states until the source of voltage reaches the stable state.
Referring to FIG. 1 of the drawings, there is shown a prior- o art disenabling circuit which comprises a level detecting circuit 1 provided with a series combination of two p-channel type field effect transistors 2 and 3 and an n-channel type field effect transistor 4 coupled between a positive voltage line 5 coupled to a power switch (not shown) and a ground terminal, and an complementary inverter circuit 6 provided with a series combination of a p-channel type field effect transistor 7 and an n-channel type field effect transistor 8 coupled between the positive voltage line 5 and the ground terminal. When an integrated circuit remains in the stable state, the positive voltage line 5 supplies all of the circuits incorporated in the integrated circuit with a positive voltage level Vcc. The level detecting circuit 1 has an output node N1 coupled between the field effect transistors 3 and 4, and an output node N2 of the inverter circuit 6 is provided between the p-channel type field effect transistor 7 and the n-channel type field effect transistor 8. A power-on disenable signal DE takes place at the output node N2 which is supplied to the component circuits. Each of the p-channel type field effect transistors 2 and 3 has a gate electrode coupled to a drain node thereof, and a gate electrode of the n-channel type field effect transistor 4 is coupled to the positive voltage line 5. The drain node of the p-channel type field effect transistor 2 is hereinunder referred to as a node N3. The p-channel type field effect transistors 2 and 3 have respective current driving capabilities ten times larger than the n-channel type field effect transistor 4 but respective threshold levels approximately equal in absolute value to the threshold level Vth of the n-channel type field effect transistor 4. Similarly, the p-channel type field effect transistor 7 has a threshold voltage level approximately equal in absolute value to the threshold voltage level Vth of the n-channel type field effect transistor 8.
Description is made for operations of the prior-art disenabling circuit shown in FIG. 1 with reference to FIG. 2 of the drawings. When the power switch is turned off, all of the nodes N1, N2 and N3 and the positive voltage line 5 are in the ground level. If the power switch turns on at time t0, the positive voltage line 5 is gradually increased in voltage level. On the way to the positive voltage level Vcc, the positive voltage line 5 excesses the threshold voltage level Vth at time t1, then the p-channel type field effect transistors 2 and 7 and the n-channel type field effect transistor 4 turn on, but the p-channel type field effect transistor 3 remains in off-state to allow the node N1 to remain in the ground level, thereby causing the n-channel type field effect transistor 8 to be in the off-state. At time t2, the positive voltage line 5 excesses the voltage level two times larger than the threshold voltage Vth, then the p-channel type field effect transistor 3 turns on to allow the node N1 to follow the positive voltage line 5. However, if the node N1 excesses the threshold voltage Vth of the n-channel type field effect transistor 8 of the complementary inverter circuit 6 at time t3, the n-channel type field effect transistor 8 turns on but the p-channel type field effect transistor 7 turns off to change the output node N2 from the positive voltage level to the ground level. Then, the power-on disenable signal DE of the active high level has been produced from time t1 to time t3 at the output node N2. After time t3, all of the transistors 2, 3 and 4 remain in the respective on-states and, accordingly, allows the node N1 to have a positive voltage level Vcc-2Vth-Vp where Vp is a positive value.
However, a problem is encountered in the prior-art disenabling circuit in insufficient reduction in current consumption. This is because of the fact that the level detecting circuit 1 continues to provide a conduction path from the positive voltage after time t3.